1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly to a technology for configuring a clock signal delay circuit.
2. Related Art
A semiconductor apparatus operates in synchronization with a periodic reference pulse signal such as a clock so as to improve an operation speed and ensure efficient internal operations. Accordingly, most semiconductor apparatuses operate using a clock supplied from an outside clock or from an internal clock generated therein as the occasion demands.
Since an external clock signal input to a semiconductor apparatus is delayed in the semiconductor apparatus, when data is output using the delayed clock signal, a problem is caused such that the output data is not synchronized with the external clock signal. Therefore, the semiconductor apparatus compensates for the phase difference between the external clock signal and the internal clock signal by using a delay locked loop (DLL) or a phase locked loop (PLL).
However, even when the phase difference between the external clock signal and the internal clock signal is compensated for by using a clock delay circuit such as the delay locked loop (DLL), a phase difference may occur due to introduction of power noise, etc. Thus, a technology capable of quickly compensating for such a phase difference is demanded in the art.